1. Field of the Invention
The present invention relates to a semiconductor memory device such as eDRAM (embedded DRAM), which is formed by cascading plural memory cell arrays in association with an interface unit such as an I/O block.
2. Description of the Related Art
For example, a conventional eDRAM is configured as shown in FIG. 27. Referring to FIG. 27, plural cascaded memory cell arrays 101-1 to 101-n are mounted on a semiconductor substrate with respect to an I/O block 100 to form eDRAM. These memory cell arrays 101-1 to 101-n and the I/O block 100 connected to an external circuit 102 are connected through a write data line 103 and a read data line 104. In writing data, write data from the external circuit 102 is inputted to the I/O block 100, and the write data is written in, e.g., the memory cell array 101-n from the I/O block 100 through the write data line 103. In reading data, read data is read from, e.g., the memory cell array 101-n to the I/O block 100 through the read data line 104, and the read data is outputted to the external circuit 102 through the I/O block 100.
Thus, a memory macro having large data storage capacity can be obtained by cascading the I/O block 100 and the memory cell arrays 101-1 to 101-n. In the eDRAM, from the design viewpoint, since it is generally difficult that the I/O block 100 is located inside the memory cell array, the I/O block 100 should be located near the external circuit 102 as shown in FIG. 27.
There is also a proposal in which a chip size of a semiconductor memory device is miniaturized by sharing a preamplifier for read and write and a write driver between the two adjacent memory cell arrays while a sense amplifier is configured in the memory cell array in forming eDRAM (for example, see Jpn. Pat. Appln. KOKAI Publication No. 2002-304881).
However, when eDRAM having the large capacity is configured by cascading the plural memory cell arrays to the I/O block, line lengths of the write data line 103 and read data line 104 is increased in order to connect the I/O block and each memory cell array. Therefore, while RC delay is increased, influence caused by the RC delay difference between the memory cell array close to the I/O block and the memory cell array far away from the I/O block cannot be neglected, which results in an obstacle to a high-speed eDRAM. In the method described in Jpn. Pat. Appln. KOKAI Publication No. 2002-304881, although the chip size can be miniaturized, the data line length cannot be prevented from increasing in relation to the increase in capacity. Therefore, the problem of the RC delay cannot also be neglected.